SystemVerilog extends Verilog's declaration capabilities by introducing packages and additional declaration spaces. These features simplify modeling complex designs while reducing potential coding errors.

Key Declaration Spaces

• Package definitions and imports
• Compilation unit ($unit) scope
• Unnamed block declarations
• Enhanced time unit specifications

Common SystemVerilog Types

Several SystemVerilog types are particularly useful for declarations:

// 4-state variable similar to Verilog reg
logic [7:0] data_byte;

// Enumerated type with named values
enum {IDLE, RUN, WAIT} state;

// User-defined type
typedef bit [15:0] word_t;

// Structure combining multiple elements
struct {
    logic valid;
    word_t payload;
} packet_t;

Package Implementation

Packages provide a structured way to share declarations across multiple modules:

package chip_defs;
    parameter VERSION = "2.0";
    
    typedef enum {READ, WRITE} cmd_t;
    
    typedef struct {
        logic [31:0] addr;
        logic [63:0] data;
        cmd_t command;
    } transaction_t;
    
    function automatic int parity_gen(input [63:0] data);
        return ^data;
    endfunction
endpackage

Package Import Methods

Package contents can be acessed in several ways:

1. Direct Reference

module memory_ctrl(
    input chip_defs::transaction_t bus
);
    always_comb begin
        if (bus.command == chip_defs::READ) begin
            // Read operation
        end
    end
endmodule

2. Selective Import

module cpu_interface;
    import chip_defs::transaction_t;
    import chip_defs::READ;
    
    transaction_t current_trans;
    
    always_comb begin
        if (current_trans.command == READ) begin
            // Handle read
        end
    end
endmodule

3. Wildcard Import

module io_controller;
    import chip_defs::*;
    
    transaction_t io_trans;
    
    always_comb begin
        case (io_trans.command)
            READ: // Handle read
            WRITE: // Handle write
        endcase
    end
endmodule

Compilation Unit Scope

The $unit space allows declarations outside modules:

// External declarations
parameter CLK_PERIOD = 10;
typedef logic [7:0] byte_t;

module timer(
    input byte_t count_val,
    output logic timeout
);
    always_ff @(posedge clk) begin
        timeout <= (count_val == 0);
    end
endmodule

Time Unit Specifications

SystemVerilog provides precise time control:

module clock_gen(
    output logic clk
);
    timeunit 1ns;
    timeprecision 100ps;
    
    initial begin
        forever #5 clk = ~clk; // 10ns period
    end
endmodule

Best Practices

• Prefer packages over $unit for shared declarations
• Use automatic tasks/functions in packages
• Specify time units explicit in modules
• Avoid variables in packages for synthesizable code