The set_driving_cell command provides precise characterization of input port drive capability by modeling the driving cell from the technology library. This approach is generally preferred over set_drive since library cell designers have detailed knowledge of internal output resistance characteristics.

To remove driving cell specifications, use the remove_driving_cell command. The BNF syntax for set_driving_cell is:

set_driving_cell
    [-lib_cell lib_cell_name] [-library lib_name]
    [-rise] [-fall] [-min] [-max]
    [-pin output_pin] [-from_pin input_pin]
    [-dont_scale] [-no_design_rule]
    [-none] [-input_transition_rise rise_time] [-input_transition_fall fall_time]
    port_list

Specifying the Driving Cell

The -lib_cell option identifies the library cell driving the input port. When a cell has multiple output pins, use -pin to specify the particular output pin.

Target Port Specification

The command applies to input ports or bidirectional ports configured as inputs. For multiple ports, enclose them in quotes or braces.

Basic Implementation

Consider a design with clock input clk and data inputs d and c:

create_clock -period 10 [get_ports clk]
set_input_delay 0.5 -clock clk [get_ports d]
set_input_delay 0.5 -clock clk [get_ports c]
set_driving_cell -lib_cell CLKINVX1 [get_ports d]

Executing this command generates a warning about design rule attribute trensfer. Use report_port -verbose to verify the driving cell assignment.

Delay and Transition Time Calculation

The tool calculates transition times using nonlinear delay models (NLDM). The additional input delay equals the difference between loaded and unloaded driving cell delays:

set_load 0.001098 [get_ports d]
report_delay_calculation -from [get_pins U2/A] -to [get_pins U2/Y]

Library Specification

Use -library to explicitly define which libraries to search for the specified cell:

set_driving_cell -lib_cell CLKINVX1 -library typical [get_ports d]

Edge-Specific Constraints

Apply driving cells to specific signal edges using -rise and -fall options:

set_driving_cell -rise -lib_cell CLKINVX2 -library fast [get_ports d]

Analysis Condition Specification

Define separate driving cells for different analyiss scenarios:

set_driving_cell -min -lib_cell CLKINVX2 [get_ports d]
set_driving_cell -max -lib_cell CLKINVX1 [get_ports d]

Pin Specification for Complex Cells

For cells with multiple output pins, explicitly specify the driving pin:

set_driving_cell -lib_cell DFFRX1 -pin QN [get_ports d]

For cells with multiple input pins, specify the input pin using -from_pin:

set_driving_cell -lib_cell CMPR42X1 -from_pin A -pin S [get_ports d]

Opreating Condition Scaling

Prevent timing values from scaling with operating conditions using -dont_scale:

set_driving_cell -lib_cell CLKINVX1 -dont_scale [get_ports d]

Design Rule Control

Suppress design rule attribute transfer with -no_design_rule:

set_driving_cell -lib_cell CLKINVX1 -no_design_rule [get_ports d]

Constraint Removal

Remove driving cell specifications using the dedicated removal command:

remove_driving_cell [get_ports d]

Input Transition Specification

Define specific input transition times for the driving cell:

set_driving_cell -lib_cell CLKINVX1 -input_transition_rise 0.5 -input_transition_fall 0.4 [get_ports d]

The tool considers timing arc monotonicity when applying these transition values.

Application Scope

The command applies only to the current analysis scenario. For multicorner-multimode designs, specify driving cells separately for each scenario.