This document provides a comprehensive review of a successful silicon tapeout project completed in May 2024. The project spanned five months from initial planning to final tapeout, representing significant progress compared to the previous year's delayed timeline.

Project Timeline and Execution

The tapeout project was executed across five distinct phases:

Planning Phace (January)

• Completed high-level macro and SoC architecture planning
• Established task asignments for team members
• Defined technical specifications and design directions
• Initiated preliminary design work across all subsystems

Development Phase (February)

• Established RTL, SystemC, and UVM development environments
• Created initial engineering framework using CMake, Makefile, and Shell scripts
• Developed a unified build system supporting RTL compilation, simulation, SystemC execution, and software driver compilation
• Began peripheral integration for RTL and SystemC components

Front-End Completion Phase (March)

• Finalized all front-end development tasks
• Resolved multi-threading issues using DPI in UVM environment
• Completed RTL and SystemC model development for critical macros
• Initiated FPGA debugging and functional validation
• Established automated trace comparison between RTL and SystemC models

Back-End Integration Phase (April)

• Completed schematic design for macro components
• Performed RTL synthesis with delays in memory compiler integration
• Utilized UVM for systematic bug detection in SystemC and RTL models
• Initiated back-end processing while maintaining parallel workflows
• Conducted preliminary GDS dry run for validation

Finalization Phase (Early May)

• Completed macro integration using LEF methodology
• Finalized digital back-end implementation
• Performed top-level DRC and LVS cleanup
• Achieved successful signoff

Technical Architecture

The project employed a modular architecture with clear separation between hardware and software components:

Directory Structure

project_root/
├── build_scripts/
├── hardware/
│   ├── fpga/
│   └── tapeout/
├── documentation/
├── systemc/
│   ├── build_exe/
│   ├── build_so/
│   ├── include/
│   ├── source/
│   └── tests/
├── software/
│   ├── project/
│   └── toolchain/
└── verification/
    ├── project/
    ├── testbench/
    └── workspace/

Unified Build System

The build automation system supports multiple workflows:

#!/bin/bash

# Unified build automation script for tapeout project
desktop_environment=0

# Check for valid parameters
if [ -z "$1" ]; then
    echo "Error: No parameters provided. Use './build_system.sh help' for usage information."
    exit 1
fi

# Display help information
if [ "$1" == "help" ]; then
    echo "Build System Commands:"
    echo "  './build_system.sh sw' - Build software driver"
    echo "  './build_system.sh sc shared' - Compile SystemC shared library for UVM integration"
    echo "  './build_system.sh sc executable' - Compile SystemC executable for standalone simulation"
    echo "  './build_system.sh sc run' - Execute SystemC simulation with terminal output"
    echo "  './build_system.sh sc log' - Execute SystemC simulation with log output"
    echo "  './build_system.sh hw fpga' - Compile and run FPGA RTL code under SoC testbench"
    echo "  './build_system.sh hw tapeout' - Compile and run tapeout RTL code under SoC testbench"
    echo "  './build_system.sh hw target debug' - Start JTAG debugging session (target: fpga/tapeout)"
    echo "  './build_system.sh hw target waveform' - Display RTL simulation waveform (requires prior simulation)"
    echo "  './build_system.sh hw tapeout synthesize' - Run synthesis with Design Compiler"
    echo "  './build_system.sh uvm compile target' - Compile UVM verification platform (target: fpga/tapeout)"
    echo "  './build_system.sh uvm simulate testcase' - Run UVM verification with specified test case"
    exit 0
fi

# Software build
if [ "$1" == "sw" ]; then
    pushd ./software/project > /dev/null
    ./build_driver.sh
    popd > /dev/null
    echo "Software driver build completed."
    
# SystemC build options
elif [ "$1" == "sc" ]; then
    pushd ./systemc > /dev/null
    case "$2" in
        "shared")
            ./build.sh shared_library
            ;;
        "executable")
            ./build.sh executable
            ;;
        "run")
            if [ -n "$3" ]; then
                ./run.sh $3
            else
                ./run.sh default
            fi
            ;;
        "log")
            ./run.sh default > simulation.log 2>&1
            echo "Simulation results saved to simulation.log"
            ;;
        *)
            echo "Error: Invalid SystemC option. Use './build_system.sh help' for usage."
            exit 1
            ;;
    esac
    popd > /dev/null
    
# Hardware build options
elif [ "$1" == "hw" ]; then
    if [ -z "$2" ]; then
        echo "Error: Hardware target not specified. Use 'fpga' or 'tapeout'."
        exit 1
    fi
    
    pushd ./hardware/$2/project > /dev/null
    
    case "$3" in
        "debug")
            start_jtag_debugger
            make vcs_debug
            ;;
        "waveform")
            make verdi_display
            ;;
        "synthesize")
            make dc_synthesis
            ;;
        *)
            make vcs_soc
            ;;
    esac
    
    popd > /dev/null
    
# UVM verification options
elif [ "$1" == "uvm" ]; then
    if [ -z "$2" ]; then
        echo "Error: UVM command not specified. Use 'compile' or 'simulate'."
        exit 1
    fi
    
    pushd ./verification/project > /dev/null
    
    case "$2" in
        "compile")
            if [ -z "$3" ]; then
                echo "Error: Target not specified. Use 'fpga' or 'tapeout'."
                exit 1
            fi
            make vcs_compile_$3
            ;;
        "simulate")
            if [ -z "$3" ]; then
                echo "Error: Test case not specified."
                exit 1
            fi
            make vcs_simulate CASE=$3
            ;;
        *)
            echo "Error: Invalid UVM command."
            exit 1
            ;;
    esac
    
    popd > /dev/null
    
else
    echo "Error: Invalid command. Use './build_system.sh help' for usage information."
    exit 1
fi

Key Technical Achievements

IP Reuse and Modular Design

• Successfully implemented macro IP with proper LIB and LEF extraction
• Enabled parallel development between digital and analog teams
• Reused existing analog IP at the top level to reduce development time
• Established clear interfaces between modules for better integration

Process Flow Improvements

• Implemented LEF-based methodology for macro integration, reducing merge time
• Integrated memory compiler earlier in the verification flow
• Established automated verification environment with UVM
• Created unified build system for all components

Technology Familiarity

• Leveraged previous experience with TSMC28 process to avoid PDK issues
• Implemented comprehensive coverage of design flow except digital back-end
• Established efficient debug methodologies for mixed-signal verification

Identified Challenges and Solutions

Project Management

• Initial timeline estimates were overly optimistic for certain components
• Solution: Implement more realistic scheduling with built-in buffers
• Recommendation: Add 10-15% contingency time to all task estimates

Toolchain Familiarity

• Initial issues with memory compiler configuration (ARM vs MC2)
• Learning curve for first-time LEF generation
• Solution: Create detailed documentation and checklists for critical tools
• Recommendation: Perform tool-specific training before project start

Verification Strategy

• Delayed integration of memory compiler models caused rework
• Solution: Earlier integration of compiler models in verification flow
• Recommendation: Include post-layout timing in initial project planning

Recommendations for Future Projects

Process Optimization

1. Further automation of manual processes in the design flow
2. Creation of standardized IP blocks for common components (LDO, PLL)
3. Development of automated I/O integration flow
4. Exploration of synthesizable PLL implementations

Capability Expansion

1. In-house development of digital back-end capabilities
2. Earlier integration of memory compiler models
3. Inclusion of post-layout timing in initial project planning

Technology Integration

1. Development of automated ADPL design flow
2. Creation of external LDO solution for power management
3. Enhancement of UVM verification environment for broader coverage

Conclusion

This tapeout project demonstrated successful execution of a complex mixed-signal design with significant improvements over previous attempts. The key to success was the modular IP approach, parallel development workflows, and comprehensive automation of build and verification processes. By addressing the identified challenges and implementing the recommended improvements, future projects can achieve even greater efficiency and predictability.