USB (Universal Serial Bus) is a standardized serial interface designed to simplify connectivity between computers and peripherals. Prior to USB, multiple incompatible connectors existed for different devices, complicating setup and requiring manual configuration. USB introduced a single, plug-and-play interface supporting diverse functions, reducing clutter and enhancing interoperability.

Host Controllers and Hardware Variants

USB host controllers implement protocol specifications and differ by generation:

• OHCI (Open Host Controller Interface): Developed by Compaq, Microsoft, National Semiconductor. Implements most tasks in hardware, easing driver development. Common in embedded systems and expansion cards.
• UHCI (Universal Host Controller Interface): Intel’s design. Offloads more work to software, lowering hardware cost. Predominantly found in PC motherboards.
• EHCI (Enhanced Host Controller Interface): Defines USB 2.0 host controller behavior down to register level. Ensures consistent feature implementation across platforms.
• xHCI (Extensible Host Controller Interface): Tailored for USB 3.0, providing register-level definitions for SuperSpeed operation.

Controller	USB Version	Speed Support	Originator	Hardware vs Software Load	Typical Use
OHCI	1.1	Low / Full	Compaq, Microsoft, NatSemi	Heavy hardware role	Embedded, expansion
UHCI	1.1	Low / Full	Intel	Heavy software role	PC motherboards
EHCI	2.0	High	Intel	Defined in spec	USB 2.0 hosts
xHCI	3.0	SuperSpeed	Intel	Defined in spec	USB 3.0 hosts

Connector Pin Assignments

USB 1.x/2.0 (4-pin)

Pin	Name	Color	Function
1	VBUS	Red	+5 V power
2	D−	White	Data negative
3	D+	Green	Data positive
4	GND	Black	Ground

USB 3.0 (9-pin plus shell)

Adds five shielded differential pairs for SuperSpeed signals alongside legacy pins.

Pin	Color	Signal (A/B)
1	Red	VBUS
2	White	D−
3	Green	D+
4	Black	GND
5–9	Blue, Yellow, Shield, Purple, Orange	SSTX± / SSRX± pairs and drain/shield

Physical Connector Types

Connectors vary by size and application:

• Standard (Type-A/B): Rectangular shapes for stationery devices.
• Mini: Smaller trapezoidal/hybrid forms for cameras, portable drives.
• Micro: Flattened versions for mobile phones and compact gadgets.

Each category includes A (downstream-facing) and B (upstream-facing) variants.

Software Stack

• Device Firmware: Manages USB protocol handling on peripherals, processing standard requests and data I/O.
• Host Drivers: OS-provided drivers handle enumeration, data flow, and class-specific logic.
• Analysis Tools: Utilities capture and decode USB traffic for debugging, e.g., hardware probes with protocol analyzers, software sniffers.

Protocol Overview

USB 2.0 remains prevalent; USB 3.0 adds SuperSpeed lanes. Protocol stack layers include electrical signaling, packet framing, transaction scheduling, and device configuration.

Key points:

• One host per bus; OTG enables temporary host negotiation between peers.
• Star topology via hubs supports up to 127 devices.
• Bandwidth is shared among devices attached to a single controller.

Signaling and Encoding

USB uses NRZI (Non-Return-to-Zero Inverted):

• Logic 0 causes signal toggle; logic 1 maintains level.
• To maintain clock sync, bit-stuffing inserts a 0 after six consecutive 1s, forcing a transition.

Sync field (0000 0001) ensures receiver alignment at packet start.

Speed Evolution

Version	Date	Target	Speed	Remarks
1.1	Aug 1998	Wired	1.5 Mbps / 12 Mbps	Low/FULL speed
2.0	Apr 2000	Wired	480 Mbps	HIGH speed
2.5	Sep 2010	Wireless	—	Wireless USB 1.1
3.0	Nov 2008	Wired	5 Gbps	SUPERSpeed

Higher speeds address growing data transfer demands while balancing EMI considerations and component costs.

Device Classes

Classes group devices by function, allowing uniform handling:

• 00h – Device-level class info in interfaces
• 01h – Audio
• 03h – HID (keyboard, mouse)
• 08h – Mass storage (e.g., flash drives)
• 09h – Hub
• FFh – Vendor-specific

Descriptor hierarchy: Device → Configuration → Interface → Endpoint.

Enumeration Process

Enumeration initializes a device:

1. Host detects connection via pull-up resistors.
2. Waits ≥100 ms for physical stabilization.
3. Issues bus reset; device responds at address 0.
4. Reads partial device descriptor.
5. Sends another reset.
6. Assigns unique address via Set Address.
7. Retrieves full device and configuration descriptors.
8. Optionally fetches string descriptors.
9. Requests appropriate driver; may re-read descriptors before Set Configuration.

Example descriptor sequence (hex):

09 02 42 00 02 01 04 80 E1
09 04 00 00 02 FF 00 00 00
09 21 10 01 00 01 22 3F 00
07 05 01 03 40 00 01
07 05 81 03 40 00 01
09 04 01 00 01 03 00 00 00
09 21 10 01 00 01 22 21 00
07 05 82 03 40 00 0A

Reconstructed meaning:

• First block: Configuration descriptor (length 9, type 02), total length 0x0042, two interfaces.
• Second block: Interface descriptor (type 04), alternate setting 0, two endpoints, vendor-specific class.
• Third block: Vendor-specific class data.
• Fourth/fifth blocks: Endpoint descriptors for interrupt OUT (address 1) and IN (addresss 129), max packet 64 bytes, interval 1 ms.
• Sixth block: Another interface descriptor for HID class (type 03).
• Seventh block: HID descriptor (length 9, HID version 1.10, country 0, one report descriptor of length 33 bytes).
• Eighth block: Additional interrupt IN endpoint (address 130).

OHCI Implementation Notes

• Suited for embedded designs due to extensive hardware offload.
• Key structures: Endpoint Descriptor (ED) holds pointers to Transfer Descriptors (TDs).
• Transactions have three phases; errors may arise per phase.
• Two transfer categories: periodic (interrupt, isochronous) and non-periodic (control, bulk).
• Communication between Host Controller (HC) and its driver occurs via registers and optional HCCA (Host Controller Communication Area).
• Lists: EDs chain TDs; processing follows arrival order. Bulk/control ED list heads reside in HC registers; interrupt ED heads reside in HCCA.

SOF (Start of Frame) tokens synchronize endpoints to host timing.