Synopsys SpyGlass RTL Verification Methodology
RTL Verification Challenges in Modern IC Design
- Increasing design complexity with advanced process nodes
- Growing verification overhead for million-gate designs
- Significant impact on project timelines and costs
Critical Verification Requirements
- Detects hazardous RTL constructs including:
- Combinatorial loops
- Finite state machine anomalies
- Metastability risks
- Identifies PPA degradation factors:
- Redundant logic structures
- Complex FSM implementations
- Unintended latch inference
- Prevents verification schedule delays across:
- Unit testing (UT)
- Integratino testing (IT)
- System testing (ST)
- FPGA prototyping
- Mitigates physical implementation risks during RTL finalization
Core Verification Capabilities
- Early-stage design analysis
- Design iteration acceleration
- Predictable implementation outcomes
Tool Architecture Overview
SpyGlass provides comprehensive RTL analysis through:
Lint Verification
- Coding style compliance
- Language construct validation
- Simulation performence analysis
- Synthesis readiness assessment
Common verification targets:
- Width mismatch detection
- Multiple signal assignments
- Floating inputs/outputs
- Embedded synthesis directives
- Incomplete sensitivity lists
- Partial conditional branches
- Unintended latch inference
Clock Domain Crossing (CDC) Analysis
- Metastability prevention (async reset synchronization)
- Multiple synchronization detection
- Signal convergence (Gray coding requirements)
- Data loss scenarios (fast-to-slow clock transitions)
Execution Modes
(1) Lint_DC
(2) Lint
(3) CDC
(4) DFT
(5) Coding_Style
(6) Power_Estimate
Project Structuer
(1) hdl/riscv_core/rtl/ # RTL source files
- riscv_core.v
- riscv_core.lst
(2) hdl/riscv_core/spyglass/ # Verification artifacts
- rpt/ # Analysis reports
- sgdc/ # Constraint files
- waive/ # Waiver management
(3) hdl/spyglass/ # Execution environment
- ./aspy # Batch mode
- ./aspy -gui # Graphical interface
