Core Concepts of SystemVerilog Assertions

1. Purpose:

   • Monitor signal timing to ensure design intent
   • Verify correct logical behavior at boundary points
   • Serve as loggging mechanism

2. Implementation:

   • Written within module blocks

3. Assertion Types:

   • Immediate assertions (non-temporal):
     • Execute like procedural statements
     • Can be used in initial/always blocks or tasks/functions
   • Concurrent assertions (temporal):
     • Clock-based verification
     • Use 'property' keyword
     • Execute in parallel with design
     • Activated only at clock edges

4. Assertion Creation Process:

   • Create boolean expressions
   • Define sequence expressions
   • Establish properties
   • Assert properties

5. Key Constructs:

   • sequence: Describes temporal behavior
     • Can be parameterized
     • Can call other sequences
   • property: Defines clocked behavior
     • Can instantiate sequences and properties
     • Supprots implication operators

6. Statement Types:

   // Assert example
   assert (condition) else $error("Verification failed");
   
   // Assume example
   assume property (prop_expr) action_block;
   
   // Cover example
   cover property (cov_expr);
   

7. Operators:

   • Implication:
     • Overlap: |-> (immediate check)
     • Non-overlap: |=> (next cycle check)
   • Delay: ##n (n clock cycles)
   • Repetition:
     • [*n]: Consecutive repetition
     • [=n]: Non-consecutive repetition
   • Sequence operators:
     • and, or, intersect
     • first_match, throughout, within

System Functions for Assertions

1. Sampling Functions:

   • $rose(sig): Detects rising edge
   • $fell(sig): Detects falling edge
   • $stable(sig): Checks signal stability
   • $past(sig,n): Gets historical value

2. Utility Functions:

   • $onehot(exp): Single-bit high check
   • $countones(exp): Counts high bits
   • $isunknown(exp): Detects X/Z states

Assertion Control Mechanisms

1. Runtime Controls:

   $asserton();  // Enable assertions
   $assertoff(); // Disable assertions
   $assertkill(); // Terminate assertions
   

2. Simulator Options:

   • -assert enable_diag
   • -assert hier=path