This article details the design and implementation of an x86 CPU power sequence controller IP. The IP core is designed for complex power sequence management of x86 acrhitecture CPUs, supporting multi-generational Intel and AMD CPU platforms. It provides complete power-on/power-off sequence control, voltage monitoring, fault protection, and other functions. The system adopts a modular design, supports configurable timing parameters, multi-voltage domain management, and inteligent fault recovery mechanisms, making it suitable for high-performance computing platforms such as servers, workstations, and industrial control systems.

Version Description:

• V1.0 2022: Initial version, only basic functions, no anomaly detection logic
• V1.1 H1 2023: Added anomaly detection logic
• V1.2 H2 2023: Improved anomaly detection and control logic

Timing Requirements to Server CPUs

x86 architecture server CPUs have multiple power rails, such as common P3V3, P1V05, P0V9, etc. If the system solution uses Eagle Stream or earlier CPUs, the power sequence of the entire system will add several groups of power rails related to the PCH. Common classifications of power sections include CPU core power, IO power, bus power, DIMM power, etc. Their power-on and power-off sequences must meet the timing requirements of the platform's PDG or EDG. Otherwise, certain bugs may emerge. Regarding the detailed meanings of power rail abbreviations or naming conventions, please study independently.

1. Simplified Power-Up Sequence Diagram (G3→S5→S0)

2. Simplified Power-Down Sequence Diagram (S0→S5)

3. Detailed Timing Diagram

FPGA-Based Control of CPU Timing

1. Three-Segment State Machine (FSM)

The core timing control logic is divided into three parts: the first part is the state transition logic; the second describes the state transition conditions and rules; the third is the output control logic. Details are as follows:

1.1 State Transition Logic (Sequential Logic)

// Sequential state transition
always @(posedge clk_sys or negedge rst_n_sys) begin
    if (!rst_n_sys)
        curr_state_reg <= ST_IDLE;
    else 
        curr_state_reg <= next_state_reg;
end

1.2 State Transition Conditions and Rules (Combinational Logic)

// Combinational condition judgment
always @(*) begin
    if (!rst_n_sys) begin
        delay_start_flag  = 1'b1;
        ms_delay_cnt      = 8'd49;
        timeout_cnt_reg   = 8'd49;
    end
    else begin
        case (curr_state_reg)
            ST_IDLE: begin
                if (config_err || pwr_fault_flag)
                    next_state_reg = ST_IDLE;
                else if (ms_delay_done) begin
                    delay_start_flag  = 1'b0;
                    ms_delay_cnt      = AUX_DELAY_G0_VAL;
                    timeout_cnt_reg   = TIMEOUT_CNT_MAX;
                    next_state_reg   = ST_AUX_G0_PWR_ON;
                end
                else 
                    next_state_reg = ST_IDLE;
            end
            
            ST_AUX_G0_PWR_ON: begin
                delay_start_flag = 1'b1;
                // (power on timeout | power run down) & (~forced power on)
                if (pwr_fault_flag)    
                    next_state_reg = ST_PWR_FAIL;
                else if ((&aux_g0_pwr_pgd | forced_pwron) && ms_delay_done) begin
                    delay_start_flag  = 1'b0;
                    ms_delay_cnt      = AUX_DELAY_G1_VAL;
                    timeout_cnt_reg   = TIMEOUT_CNT_MAX;
                    next_state_reg   = ST_AUX_G1_PWR_ON;
                end
                else
                    next_state_reg = ST_AUX_G0_PWR_ON;
            end
                
            ST_AUX_G1_PWR_ON: begin