Role of .sgdc in SpyGlass CDC

SpyGlass CDC relies on .sgdc constraint files to identify clock sources, reset polarity, and the clock-domain association of data-carrying ports. With accurate constraints, the tool enumerates cross-domain paths and classifies them correctly, minimizing false errors and warnings.

Why author constraints even if auto-generated

• Tool-generated constraints are often incomplete or overly generic.
• Manually curated .sgdc files correct misidentified clocks/resets and add missing data-domain annotations.
• Detailed constraints substantially reduce CDC noise and review effort.

What must be constrained

• Top-level and hierarchical input ports: identify clocks, resets, and assign data ports to their driving clock domains.
• Black-box interfaces: constrain both inputs and outputs, since CDC analysis cannot infer logic inside a black box.
• Module outputs that are not black boxes general do not require explicit constraints unless the port belongs to a black box.

Core commands

• current_design sets the analysis root.
• clock -name <hier_clk> -domain <domain_id> [-tag ] declares a clock and binds it too a domain.
• reset -name <hier_reset> -value {0|1} defines reset polarity (0 for active-low, 1 for active-high).
• abstract_port -module -ports <port_expr> -clock <hier_clk> assigns data ports to a clock domain via a specific clock.

Authoring guidelines

• Use hierarchical signal names in clock/reset declarations (e.g., top.sub.clk).
• Do not use wildcards to buses. Explicitly write full ranges, e.g., data[1023:0], not data[*].
• Avoid expressions in bit ranges. Use data[1023:0], not data[1024-1:0].
• Constrain every relevant black-box port (inputs and outputs) to the correct domain.
• Keep domain names stable and meaningful (e.g., HOST, CORE) and optionally tag clocks for readability.

Example .sgdc

current_design "eth_mac"

# Clocks and domains
clock -name "eth_mac.host_clk"  -domain HOST -tag HOST
clock -name "eth_mac.core_clk"  -domain CORE -tag CORE

# Resets (polarity via -value)
reset -name "eth_mac.host_rst_n" -value 0
reset -name "eth_mac.core_rst_n" -value 0

# Data ports in HOST domain
abstract_port -module eth_mac -ports cfg_wr                 -clock eth_mac.host_clk
abstract_port -module eth_mac -ports cfg_rd                 -clock eth_mac.host_clk
abstract_port -module eth_mac -ports cfg_addr[12:0]         -clock eth_mac.host_clk
abstract_port -module eth_mac -ports cfg_wdata[31:0]        -clock eth_mac.host_clk

# Data ports in CORE domain
abstract_port -module eth_mac -ports tx_payload[1023:0]     -clock eth_mac.core_clk
abstract_port -module eth_mac -ports tx_sop                 -clock eth_mac.core_clk
abstract_port -module eth_mac -ports tx_eop                 -clock eth_mac.core_clk
abstract_port -module eth_mac -ports tx_valid               -clock eth_mac.core_clk

# stats_blk is a black box: constrain both inputs and outputs
# Inputs
abstract_port -module stats_blk -ports mem_wr               -clock eth_mac.host_clk
abstract_port -module stats_blk -ports mem_rd               -clock eth_mac.host_clk
abstract_port -module stats_blk -ports mem_addr[12:0]       -clock eth_mac.host_clk
abstract_port -module stats_blk -ports mem_wdata[31:0]      -clock eth_mac.host_clk

# Outputs
abstract_port -module stats_blk -ports mem_rdata_vld        -clock eth_mac.host_clk
abstract_port -module stats_blk -ports mem_rdata[31:0]      -clock eth_mac.host_clk

Additional tips

• If multiple clocks reach a module, split abstract_port statements by port subsets per clock.
• For replicated interfaces, list each bus explicitly with its exact width.
• Keep the .sgdc under version control alongside RTL so constraint changes track interface changes.